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		gem5: ISCA 2006 
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  <h1 class="title">ISCA 2006</h1>
  <br>
  <p>Using the M5 Simulator ISCA 2006 Tutorial Sunday June 18th, 2006</p>

<h2 id="introduction">Introduction</h2>

<p>This half-day tutorial will introduce participants to the <a href="/">M5 simulator
system</a>. M5 is a modular platform for computer
system architecture research, encompassing system-level architecture as
well as processor microarchitecture.</p>

<p>We will be releasing version 2.0 of M5 in conjunction with this
tutorial. Features new in 2.0 include:</p>

<ul>
  <li>Multiple ISA support (Alpha, MIPS, and SPARC)</li>
  <li>An all-new, execute-in-execute out-of-order SMT CPU timing model,
with no SimpleScalar license encumbrance</li>
  <li>All-new, message-oriented interface for memory system objects,
designed to simplify the development of non-bus interconnects</li>
  <li>More extensive Python integration and scripting support</li>
</ul>

<p>Because the primary focus of the M5 development team has been simulation
of network-oriented server workloads, M5 incorporates several features
not commonly found in other simulators.</p>

<ul>
  <li>Full-system simulation using unmodified Linux 2.4/2.6, HP Tru64 5.1,
or <a href="http://l4ka.org/projects/pistachio">L4Ka::Pistachio</a>) (Alpha
only at this time… coming in the future for MIPS and SPARC)</li>
  <li>Detailed timing of I/O device accesses and DMA operations</li>
  <li>Accurate, deterministic simulation of multiple networked systems</li>
  <li>Flexible, script-driven configuration to simplify specification of
complex multi-system configurations</li>
  <li>Included network workloads such as Apache, NAT, and NFS</li>
  <li>Support for storing results from multiple simulations in a unified
database (e.g. MySQL) for automated reporting and graph generation</li>
</ul>

<p>M5 also integrates a number of other desirable features, including
pervasive object orientation, multiple interchangeable CPU models, an
event-driven memory system model, and multiprocessor capability.
Additionally, M5 is also capable of application-only simulation using
syscall emulation.</p>

<p>M5 is freely distributable under a BSD-style license, and does not
depend on any commercial or restricted-license software.</p>

<h2 id="intended-audience">Intended Audience</h2>

<p>Researchers in academia or industry looking for a free, open-source,
full-system simulation environment for processor, system, or platform
architecture studies. Please register via the
<a href="http://www.ece.neu.edu/conf/isca2006">ISCA 2006</a> web page.</p>

<h2 id="tentative-outline">Tentative Outline</h2>

<ul>
  <li>M5 structure
    <ul>
      <li>Object structure
        <ul>
          <li>Intro to SimObjects</li>
          <li>Object builder</li>
          <li>Configuration language</li>
          <li>Specialization using C++ templates</li>
          <li>Object serialization (checkpointing)</li>
        </ul>
      </li>
      <li>Events</li>
    </ul>
  </li>
  <li>CPU models
    <ul>
      <li>Simple functional model</li>
      <li>Detailed out-of-order model</li>
      <li>Sampling and warm-up support</li>
    </ul>
  </li>
  <li>Memory &amp; I/O system overview
    <ul>
      <li>Cache models</li>
      <li>Interconnect models (busses, point-to-point networks)</li>
      <li>Coherence support</li>
      <li>I/O modeling
        <ul>
          <li>Programmed I/O (uncached accesses)</li>
          <li>DMA I/O</li>
        </ul>
      </li>
      <li>Ethernet model
        <ul>
          <li>NIC device models</li>
          <li>Linux driver</li>
          <li>Link layer model</li>
        </ul>
      </li>
    </ul>
  </li>
  <li>Full-system modeling
    <ul>
      <li>Building disk images</li>
      <li>Console and PAL code</li>
      <li>Running benchmarks via system init scripts</li>
      <li>Target kernel introspection support</li>
    </ul>
  </li>
  <li>Statistics
    <ul>
      <li>Built-in statistics types</li>
      <li>Adding new statistics</li>
      <li>Using the database back end
        <ul>
          <li>Setting up a results database</li>
          <li>Using scripts to generate reports and graphs from the
database</li>
        </ul>
      </li>
    </ul>
  </li>
  <li>Debugging techniques
    <ul>
      <li>Built-in debugging support
        <ul>
          <li>Tracing</li>
          <li>Runtime checking</li>
          <li>Gdb hooks</li>
        </ul>
      </li>
      <li>Debugging target code (including kernels) using remote gdb</li>
    </ul>
  </li>
  <li>ISA description language
    <ul>
      <li>Adding your own instructions to the ISA</li>
      <li>Adding support for new ISAs</li>
    </ul>
  </li>
</ul>

<h2 id="speakers">Speakers</h2>

<ul>
  <li>Steven K. Reinhardt is an associate professor in the EECS Department
at the University of Michigan, and a principal developer of M5. He
received a BS from Case Western Reserve University and an MS from
Stanford University, both in electrical engineering, and a PhD in
computer science from the University of Wisconsin-Madison. While at
Wisconsin, he was the principal developer of the Wisconsin Wind
Tunnel parallel architecture simulator.</li>
</ul>

<!-- end list -->

<ul>
  <li>Nathan L. Binkert received his Ph.D. candidate from the EECS
Department at the University of Michigan, and a principal developer
of M5. He received a BSE in electrical engineering and MS in
computer science both from the University of Michigan. As an intern
at Compaq VSSAD, he was a principal developer of the ASIM simulator,
currently in use at Intel and is currently with Arbor Networks.</li>
</ul>

<!-- end list -->

<ul>
  <li>Ronald G. Dreslinski is a Ph.D. student in the EECS Department at
the University of Michigan, and a developer of M5’s memory system.
He received a BSE in electrical engineering, a BSE in computer
engineering, and a MSE in computer science and engineering all from
the University of Michigan.</li>
</ul>

<!-- end list -->

<ul>
  <li>Kevin T. Lim is a Ph.D. student in the EECS Department at the
University of Michigan, and the developer of M5’s detailed CPU
model. He received a BSE in computer engineering and an MSE in
computer science and engineering from the University of Michigan.</li>
</ul>

<!-- end list -->

<ul>
  <li>Ali G. Saidi is a Ph.D. candidate in the EECS Department at the
University of Michigan, and wrote much of the platform code for
Linux full-system simulation. He received a BS in electrical
engineering from the University of Texas at Austin and an MSE in
computer science and engineering from the University of Michigan.</li>
</ul>

<p><strong>NOTOC</strong></p>


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